1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods of inspecting semiconductor workpieces for surface defects using chemical exposure of resist films.
2. Description of the Related Art
Large scale integrated circuits now routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous individual components are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
In addition to the one or more metallization layers, modern integrated circuits also incorporate numerous routing-restricted interconnect levels commonly known as local interconnects and contacts. Local interconnects and contacts are used for short metallization runs such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure in the integrated circuit.
A method frequently employed to form contact structures involves a damascene process in which the substrate containing the integrated circuit is coated with a layer of dielectric material that is lithographically patterned and etched to form contacts or vias in the dielectric layer where the contact structures will be formed. Thereafter, the contact material, or materials if a laminate structure is desired, is deposited over the dielectric layer. The goal of the deposition process is to fill the vias as completely as possible. Finally, a planarization process is performed to remove the excess conducting material from the dielectric layer and leave only the filled vias.
A variety of defects may arise during processing of interlevel dielectric and metallization layers. For example, portions of the upper surface of the interlevel dielectric layer may crack as a result of differential thermal stresses or rip-out during chemical-mechanical-polishing xe2x80x9cCMPxe2x80x9d. In addition, contaminant particles may be left or deposited on the interlevel dielectric layer following CMP of the bulk-deposited metallization film. In either case, the defect can interfere with subsequent lithography processing on the interlevel dielectric layer, via etching or conductor deposition. Moreover, the problem is not limited to interlevel dielectric-contact formation. Indeed, the successful application of stacked films often requires a relatively pristine underlying surface upon which each successive layer is formed. However, the presence of defects in the surface of an underlying layer may cause the overlying film to later delaminate and lead to device failure.
Therefore, accurate, reliable and early defect inspection is vital to successful semiconductor fabrication. It is desirable to be able to identify film surface defects as early in a given process flow as possible since continued production processing of wafers that will ultimately have to be scrapped or reworked represents waste in terms of both fab time and material. As an example, undetected surface defects in an interlevel dielectric layer may result in poor contact lithography or etching. In such circumstances, the time and material involved in the contact lithography, e.g., the photoresist application, exposure, development, and contact etch will be wasted.
Currently, inspection for surface defects is performed with various types of scanning tools. Some of these employ optical scanning, while others utilize laser scanning. Many conventional contact defect scanning techniques utilize die-to-die comparison, although die-to-database comparing is also sometimes used.
A limitation associated with conventional surface defect inspection is tool sensitivity. Many types of defects are too small for the inspection tool to resolve. Other types may elude detection because their geometries mimic patterned features in the film. Still others may go undetected because they occur relatively infrequently across the surface of a given film. As a time savings measure, many metrology tools are set up to examine only certain sample portions of a given film. Thus, defects capable of causing device failure may pass inspection if they do not happen to fall within the designated sample portions of the film.
Another limitation associated with some conventional defect inspection methods is destruction of the scanned surface. Techniques such as transmission electron microscopy and time of flight secondary ion beam spectroscopy can identify certain kinds of defects, but also result in the destruction of the scanned structure.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of inspecting a surface of a semiconductor workpiece for defects is provided that includes applying a negative-tone photoresist film to the surface and baking the negative-tone photoresist film to release solvent therefrom and to facilitate release of catalyzing substances held by the defects into the negative-tone photoresist film. The catalyzing substances react chemically with at least one moiety of the photoresist film to thereby lower the solubility of one or more portions of the negative-tone photoresist film in a developer. The negative-tone photoresist film is developed with the developer and the surface is inspected for the portions of the negative-tone photoresist film remaining after the developing process. The remaining portions of the negative-tone photoresist film are indicative of the locations of the defects.
In accordance with another aspect of the present invention, a method of inspecting a surface of a semiconductor workpiece for defects is provided that includes applying a positive-tone photoresist film to the surface and baking the positive-tone photoresist film to release solvent therefrom and to facilitate release of catalyzing substances held by the defects into the positive-tone photoresist film. The catalyzing substances react chemically with at least one moiety of the photoresist film to thereby increase the solubility of one or more portions of the positive-tone photoresist film. The positive-tone photoresist film is developed with the developer and the surface is inspected for the dissolved portions of the positive-tone photoresist film appearing after the developing process. The dissolved portions of the positive-tone photoresist film are indicative of the locations of the defects.
In accordance with another aspect of the present invention, a method of inspecting a dielectric film on a semiconductor workpiece for defects is provided that includes applying a photoresist primer to the dielectric film and applying a negative-tone photoresist film to the dielectric film. The negative-tone photoresist film has actinic sensitivity to deep ultraviolet radiation. The negative-tone photoresist film is baked to release solvent therefrom and to facilitate release of acidic substances held by the defects into the negative-tone photoresist film. The acidic substances react chemically with and thereby lower the solubility of one or more portions of the negative-tone photoresist film. The negative-tone photoresist film is developed with the developer and the dielectric film is inspected for the portions of the negative-tone photoresist film remaining after the developing process. The remaining portions of the negative-tone photoresist film are indicative of the locations of the defects.